How ESD affects Electronic devices?

Typically electronic devices eg integrated circuits (IC), ASICs (Application Specific ICs) and others have very tiny geometrical structures made in the very small submicron range in silicon. Modern electronic devices are susceptible to be damaged by electrostatic discharges due to the above outlined dimensions. The susceptibility (measured in volts) of electronic devices likely to experience damage is dependant upon the material used on its manufacturing process and more importantly of the size of their micro structures, as a guide, TTL devices would be less susceptible, in the 1000 to 2500 V range and MOSFET or VMOS the more susceptible in the 30 to 1800 V range.

But all that is only the start because as the miniaturisation of the basic silicon components in the ICs continue the ESD problem can only be worsen. This is the results outlined by the Moore’s Law (Gordon Moore in 1964, said that the number of transistors that we can fit into an integrated circuit will double every 18 months). On a conference held in Sydney (Australia) early in 2001 Jeff Krisa, Intel’s representative said they see no problems to continue improvement on manufacturing of ICs from silicon. In fact he said Intel intended to manufacture ICs for the Pentium III and IV high end processors with 0.13microns technology by August 2001 (this actually occurred around Jan’2002 where the 2Ghz Pentium 4 moved from 0.18 to 0.13 microns) and they plan to move to 0.10microns in 2003 and 0.07microns in 2005 (Jeff said that technology for 0.07microns is technically achievable). Further Jeff said that in addition to reducing even further the size of the microstructures they are reducing operational voltages and improving in current drives, however the minimum operational voltage in Silicon is around 1V.

But is not only Intel’s opinion. The Semiconductor Industry Association (SIA) is pushing the manufacturing industry with a drastic plan of size reductions eg to 0.09 microns by 2004 and 0.022 microns by 2016. The arguments given by the Association is a perceived dramatic improvement in performance of the chips and most importantly a reduction in prices, the latter due to savings by not needing to increase power, hence not having to experience an increase in heat dissipation. The industry will produce much more circuits out of a similar size silicon wafer.

Also AMD has moved all its manufacturing processes on their Fab 30 plant in Dresden Germany to 130nm technology, AMD is expecting to have all their wafers by the end of 2002 on the new technology. However, according to other scientific sources there is another barrier approaching rapidly against the above described trend, this is the natural laws of physics in silicon where it is envisaged that soon a threshold will be reached where electrons could tunnel through the tiny insulating walls (at around 1.5nm) allowing unpredictable leakage current to produce unexpected transistor switching.