Latent Failure

Electronic devices may receive ESD discharges which will not fail the device immediately but at some time later (perhaps years). After a device experience an ESD hit and has not failed catastrophically still may be degraded and hence its lifespan will be somewhat shortened. Latent damage is cumulative in nature as every time a discharge hits the device, it becomes weaker and more prone to terminal collapse, the per design component characteristics would have worsen.

Unfortunately there is no way of detecting a latent fault in a device as it may pass all test and after extensive burn-in periods, unless of course we apply some destructive type of testing analysis. In fact the device is expected to be at its worst when arriving to the purchase’s premises as an assembled piece of equipment, it would have gone through many potential statics events exposures eg the many stages of the production line of the device, final testing, packing, PCB assembly manufacturers, delivery subcontractors, etc…

When a component fails catasthrophically because of a latent fault event, the function of a PCB will not necessarily fail. So each PCB has a critical path that once clearly identified should tell us exactly the different components that are really critical, any of these failing can fail the PCB function. Also this critical path will have some electronic components that are more susceptible to ESD events than others, this is were a PCB designer will concentrate his attention and these weaker components are to be further protected as to raise their ESD operational life span, the designer will use fail safe circuits, try alternative components to achieve the same aim, redundancy circuitry and perhaps more ESD resilient components. There are different classes of devices, they are categorised according to their resilience to ESD discharges. The more susceptible (class 0)to ESD the component is the more expensive it becomes to protect it.